Hardware Acceleration for ZK Cryptography w/ Leo Fan (Cysic)

**Speaker A:** Foreign. **Speaker B:** Hello and welcome back to the Strange Water Podcast. Thank you for joining us for today's conversation. There is a lot to love about zero knowledge cryptography. On this show, we really only focus on using ZK as a tool to compress computation and to enable decentralized computing networks. But we could easily spend just as much time on ZK's implication for privacy or digital identity or any of the undiscovered applications that we're inevitably going to find for zk. We already see so much promise, and we're in a world where groundbreaking research is released faster than Apple can get out a new iPhone. But behind all the optimism and the entrepreneurial energy behind ZK today, there's a more frustrating side of the technology. The concepts are impenetrable and the tooling is hard to find and even harder to use. And what few primitives that do exist are a nightmare to integrate. And really, that's just the start. Again, it can be frustrating, but I guess that's always the case when you're deploying research hot off the Forge. But we are here today to focus on one particular pain point. **Speaker A:** Performance. **Speaker B:** Even the best ZK systems right now take so long to run that they're practically useless in real world applications. Just like the Internet would be functionally useless and largely ignored if we could only transfer one or two sentences in like an hour. We would be in trouble if the performance of ZK systems was limited to what we had today. Today's guest is Leo Fan, founder of CISIC and a big reason why the ZK community is so confident that we will overcome the performance problem that we are racing to build empires here. CISIC is working on creating hardware specifically etched with the ZK primitives that will power our trustless future. This episode is a comprehensive look at what it means to write applications into silicon and metal, including an overview of how chips are made and reflections on how chip manufacturing factors into geopolitics. I won't spoil the numbers for you here, but suffice it to say that once you hear Leo tell us how dramatically they can already accelerate ZK proofs, you'll begin to understand just how it feels to be at the beginning of ZK's Moore's Law Frenzy. One more thing before we begin. Please do not take financial advice from this or any podcast. Ethereum and ZK will change the world one day, but you can easily lose all of your money between now and then. All right, let's go. Leo, thank you so much for joining us for the Strangewater podcast. **Speaker A:** Thanks a lot for having me here. **Speaker B:** Of course. So before we dive into ZK and get into hardware, I'm a huge believer that the most important part of every conversation are the people involved. So with that is background, can you give us a little bit about who you are, how you found zk, how you found hardware and yeah, just tell us a little bit about yourself. **Speaker A:** Thanks a lot. Yeah, so my name is Neil Fan, I'm a co founder of Seisic and before Seisic I got my PhD from Cornell. So like yeah, from Cornell in cryptography. So I'm more like a software like algorithm guy. And before Cornell like I did some time. Yeah, I indeed spent some time in China doing some bitcoin. Yeah. So after Cornell like I spent some time in a blockchain company called Algorand. So while I was at Algorand and I helped with Algorand state proof. So Algorand state proof is essentially a ZK proof can be used as a cross chain bridge between Algorand, ACM and Algorand's. Anonymous. So when we finished the POC for that part, it was April 2022, I found the post generation time for, for the ZKP proof there. It's quite long. I try a lot on the software, on the algorithms, but it didn't improve a lot on the proof generation time. So I think maybe we can design some specialized hardware as what we did for the bitcoin mining before. So we designed some specialized hardware for that to make sure the proof generation time is acceptable. But I do not. Yeah, so at that time I didn't know too much about the market. So I talked to my friend inside ZK complaints and they promised me there will be like a huge demand for your hardware if you like succeeding in doing that. So that's like why we started siseq. So SISEQ is a hardware design company for zkp. We aim to design some specialized hardware like the, to accelerate the proof generation for zigp. And right now we are in the phase of using FPGAs and also GPUs to do the work. **Speaker B:** So we'll unpack and really dig into what it means to be using FPGAs and the roadmap to ASICS and then what that'll mean for the industry. But while we're still in your background here, can you tell us the story of how you found Bitcoin and why you decided that this was something interesting and not something to run away from? **Speaker A:** Right. Actually kind of like, yeah, so like I. Yeah, before Cornell, like I spent some time in China also, like doing some research on cryptography. Yeah. So like, I happen to know a friend of a friend, like in Japan. His name is actually Okamoto. So like, when I first read the bitcoin white paper, the names Nakamoto. I think maybe he uses pseudonym to write that paper. So I read it. It was sometime in 2011, I think, or 2010 or 2011. So it was like a while back. Yeah. So that's why I learned this paper, I think. Yeah. So we actually, we try to solve like the cryptographers, they try to design some ecach long ago. But the previous post is quite maybe boring, I would say. And this is like Santosh, he come up with a very nice idea. I'm not sure if it's here or she would like it. Yeah. So. But they came up with a very nice idea to design this peer to peer payment network. I thought that was very, very interesting. And also it has some relationship with my research. And I happen to know someone in China at that time was doing some bitcoin mining or like I saw and like join them. Like it was like 2011 or 2012 at that time. Yeah. **Speaker B:** So I think like today in 2023, it's really, really clear that cryptography and everything that we're working on is like, it's so new and we need to like kind of get it right. But once we get it right, it's going to have implications on all sorts of industries and all sorts of computer science problems. I think one of the more subtle but more cool things about the bitcoin white paper moment is that was the moment where maybe not you as a real cryptography researcher, but us on the layer above that we realized that, oh my God, for the first time that I've ever realized there's another use case for cryptography other than just encrypting messages, tighter and tighter and tighter. And so I guess, like my question for you is, in that moment when you know your friend who you think might be satoshi is like exposing you to this and you're getting more and more interested, what percentage would you say attracted you of like the ideological, the decentralized censorship, like those kinds of things, and what part of it, like was truly about the tech and implementing cryptography in a way that provides like brand new systems? **Speaker A:** Yeah. So I would say it's a technique in the paper, like first draw my attention. Yeah. So like previously, like, people all the design this like ecache system, they are centralized system. And if people want to decentralize it, there is always a way to circumvent, to get it centralized. Yeah, so like at least in the very beginning, whereas for the Bitcoin white paper I found it like fascinating due to the techniques to help decentralize this system. It was quite interesting to see that idea. And also maybe after some time I realized maybe the decentralization will also be very helpful for us to get around the censorship and all the other things. It was a technique that drew my attention. Then I found maybe the ethos or the idea like in the blockchain community somehow aligns also with maybe some part of me. So like. **Speaker B:** Yeah, yeah, no, no, that makes sense. And again, while we're still in the background section of this conversation. So you found yourself at Algorand and I think that you might disagree with this. Feel free to. I think that many of us in this industry really believe that kind of the point of this industry is to, to build out Ethereum and then build from this core shared backbone settlement layer. And I think something that a huge thing that we saw in the last cycle are these alt L1s, which for me I don't really see a role for in the long term story of cryptocurrency and digital property. But the cool thing about all L1s is they provide a playground and an entirely different innovation space for like blockchain related stuff that doesn't screw with, you know, our perfect, our like precious Ethereum. So with that kind of as context, like can you talk a little bit about you found yourself at Algorand? If there's an interesting story of how you found it, let us know. But what did you think that Algorand was doing that was really cool and really interesting that you think is worth like that you took with you in the work that you're kind of applying now? **Speaker A:** Yeah. So I would like to talk first a little bit about the ICO summer back in 2016, 2017. Yeah, so I was somehow also involved in that period of time. So all these layer ones as you mentioned, they try to come up with a better throughput, like a higher throughput, better efficiency to kill Ethereum. But yeah, if you can say, I would say maybe, yeah, maybe some of them will have higher performance over Ethereum. But in the end it's all about the community. And the community, they can support Ethereum, they will come up with different steps on Ethereum to enhance it. And Ethereum also itself got involved from the very beginning. So when I was at Cornell, actually We met research group, met Vitality quite often back in 2015, 2016. There is cryptocurrency bootcamp at Cornell and we somehow interact with Vitalik at that time. And as you can see, some of the Cornell professors also come out to develop some layer ones, try to beat Ethereum on the efficiency. Also like the Acurant is also founded by Silver McCartney who is a twin award and also MIT professor. Yeah, so like actually like I think like we actually we the professors, like they bring a lot of the research from the academia to the industry. Yeah, this like for instance you can get higher throughput using some of the techniques proposed by my advisor Inishi. And also you can use maybe VRF to select the block producer. So this idea was by Mikani, I guess maybe the professors provides more formally defined and more rigorously proving idea to the world. Maybe some of them are not very efficient or like the. When the professors they implement these ideas in the community world, they are not very good at that. But the input provided by the professors are quite important to the community. **Speaker B:** Yeah, that makes a lot of sense. So it is so clear if you're working in proofs or ZK proofs at all that like Algorand or beyond, like these things are really cool, but it's really, really hard to like get them done right. And there's this, all these pieces around the tooling and the frameworks and just like the difficult pieces around getting like advanced Moon math into your computer. But then as is very clear, like there's a whole aspect of performance. So we'll, we'll move into this piece now. But just like as a preface, when you're running these proofs and you're seeing that they're running really slow, how much background do you personally have in hardware and how much do you see in this moment that like hardware is a real answer here or is that become part of the solution as you, you know, like socialize and communicate more and more with other people that this is the problem problem and we need to come up with a solution. **Speaker A:** Yeah. So only speaking I don't have much background in hardware engineering. The thing or the perspective I have for these algorithms is to say first how parallel this algorithm can be and the second part is what is the interaction between the processor and the memory during the computation. So if I can figure out these two parts, then I can say maybe also like very ad hoc about the hardware friendliness of this algorithm. So that's my first impression on ZK when I take a look at the ZK algorithm. I know there are a lot of algorithms, so I first focus on this major components like the multiscalar multiplication, number theory, transform and the pathetic Merkle tree I saw. I guess maybe the majority of them can be very parallelizable on the processors and although some of them have quite weird memory access patterns, but we can always using some shuffle or other techniques to improve on that. And if we can run this algorithms in massively parallelizable modes, then we can borrow the idea like we developed for the bitcoin mining. Like recalling the bitcoin mining machine. It doesn't have just one chip, it actually has more than 100 chips in the mining machine to accelerate that. And we can do almost the same thing, although we need to deal with the flexibility and also the. Yeah, so like the naked skin, they are not stable yet. So like we need to handle the programmable part also as well. **Speaker B:** Got it. So last question before I ask you just what is cisic? And can you describe me what you're trying to do? But just I think a necessary piece of background is can you help me and help the audience understand, let's just say the spectrum of CPU to F, G, gpa, FPGA to asic and why on that spectrum? Like basically what do those different terms mean and why as you move closer to ASIC do you get more efficiency but what trade offs are you making as you move over there? **Speaker A:** Okay, yeah, so I would say like we will treat the CPU as maybe as like Swiss army knife. It's like very powerful, it can handle a lot of functionalities. And the fpga. FPGA is less powerful with army knife, but it doesn't have that functionality. Which means it can be more focused on doing maybe just something and you have more ownership on this fpga. You can program it to do something and you do not need to waste any resource on the FPGA to do the other functionality that you don't care about. Okay, so that's the fpga and ASIC is basically a hammer. It's a very powerful machine, but it can be used to do only very limited sims. It's like. Yeah, which means the clock frequency of the ASIC will be like much higher than fpga, but it doesn't have too much flexibility inside. You can do one thing or like maybe one or two things very, very well, but it cannot be expanded to do a lot of things. **Speaker B:** And so is it fair to think of if a CPU is the Swiss army knife, it's general purpose, it can do anything that any computer can do. And an ASIC is a hammer. It is very specific. It can only do one thing. Is it fair to think of a FPGA as like. It's a programmable chip that virtually can act like an asic, but the cool part is you have the flexibility to change it a little bit. So you get the flexibility and a little bit of the performance. But that's why it sits like right in the middle. So first of all, is that correct? **Speaker A:** Yes, yes, that's correct. Yeah, it's right in the middle. And you can basically program the chip to do something that you like and you don't need to rest the resource on the chip to like. Yeah. Since like in the, in the CPU it always have some, it always reserves some resource to do other things and you can only account for maybe a minority of the CPU to CPU chips to do your computation. Yeah. **Speaker B:** And again, I think this is so critical to what Sisig is building, so I'm just going to hammer it home. The idea here is that like a cpu, because it's general purpose, has to spend a lot of overhead and a lot of non useful computation setting up the computation that wants to be done. Let's say I want to do one plus two. The CPU first has to say okay, we're going to do addition. Okay, there's going to be between two digits. Okay, okay, okay. All right, now we're going to do one plus two. Whereas an ASIC has none of this generalizability. All it knows how to do is take an input, take a second input and do the plus. And if you ever want to do multiplication or division on that chip, you're screwed. Like it's in the silicon that it can only do the addition. But the good news is that is you have zero overhead. And it's that loss of overhead which allows asics to like perform basically the same operations but like orders of magnitude faster than a cpu. Is that correct? **Speaker A:** Yes, that's correct. Yeah. So like in asic you basically like hotwire all these circuits on the, the chip and you cannot do like to do something like you haven't planned on the chip. So that's some like limitation on the, on the asic. But on the good side it's like very performant and it's basically can run on wrong things like in massive polarizable way to improve the efficiency. And also things like, and also it's kind of quite cheap. I can compare with designing or taping out a cpu. So you control all the resources on The ASIC chip, how many pieces you want to put on the ASIC and how much memory you want to have on that so you can control the budget and you just tenor something for yourself and you just pay for. Oh yeah, yeah, you just, you just pay for that. **Speaker B:** Yeah. And I definitely want to spend some time talking with you about the manufacturing process. I mean we live in 2023. Like all anyone on a global scale is talking about is chip manufacturing. So we'll get there in a minute. But I think we've got enough background to like. Leo, can you tell us like what is cisic? What is the goal? And yeah, like what are you trying to do with for ZK technology? **Speaker A:** Okay, yeah, so like for sesig, our end goal is to design some hardware that can, that can generate the ZKP proof in real time. So which means like we want to generate the ZKP proof for all the major proof system and for all the major circuits such as like the Zkevent circuits, the ZKML, the ZKGPT2 or like some also per second hash circuit in less than one second. So that's our goal and we also want to achieve this goal in a cost effective way. We don't want to spend maybe a half million to just produce just one machine which is capable to do that. Actually we want to reduce the cost for that machine to be comparable with the current, the mainstream GPU card, the 1490 or maybe the 1590 Jeep card that will be released next year. So that's something that we want to achieve the best performance in a cost effective way for doing the ZKP generation. So that's the go for cisic. **Speaker B:** Cool. And then is the goal for CISIC to be creating chips that are bought by maybe not consumers, but for example, I'm someone who's an ethereum home staker and so I'm willing to dedicate home resources to something like are CISX chips aiming to be in that kind of dedicated hobbyist market or are we looking at the same as the Nvidia high end chips? They really only belong in data centers and those kinds of chips. **Speaker A:** Yeah, so that's something we want to achieve. Our machine can be bought actually by normal individual by this like enterprise or like the high end one. Yeah, so then like we just want to at least replace the majority of the GPU cards that is used in the zkp. Proving currently with our machine like we. Since like when people are talking about these like chips or like the mining machine, they have our impression that they could be like very expensive. But actually that's not. Maybe that's correct for now, but with Ethics Chip, we want to change the impression. We want to see if you use our machine to do ZK proving like actually you can get your money back in maybe acceptable period of time. Yeah, that's something that we want to achieve. **Speaker B:** Cool. And I think we can talk a little bit later about what you just said is very interesting because that's circling back the actual hardware you're creating with some of like the interesting crypto economic systems that are being built on the blockchain side. So let's circle back to that. But I think the really cool thing about like what you're building is like that there's a lot of problems with ZK technology today. We've talked about. Right. There's the implementation details and then there's the, the actual performance. And today performance is like so rough that, you know, we're in the dial up era of like ZK technology. Right. The. But like, let's focus for a minute on that actual application development and, and how that marries up with hardware. So the ZK very, very complicated. Let's take one example, like Plonk Plunk is really like this giant protocol. And in it there's like a bunch of different things that could be considered zk. There's a bunch of different things that's just, I don't know, overhead or transformations, let's say. And then like within Plonk, there's a commitment scheme. We'll just use KZG commitments for a second. Within KZG commitment, there's some things that are considered overhead, there's some, there's some things that might change in the future, there's some things that won't. And we can keep going all the way down the stack until we get to the most basic primitives. Things like multimatrix multiplications or FFTs or the core mathematical primitives. And I guess just to cut to the chase, my question for you is when you're looking at holistic ZK systems, how do you think about designing hardware that is really applicable and can really accelerate these systems, but doesn't tie your users and yourself as a company to like, technology that is so quickly changing and like, might be outdated within, I don't know, like a week. **Speaker A:** Right? Yeah. So as you, as you said, like, if you like dive it in deeper, you say like you start with Plank and then you go down to the like polynomial commitment scheme. And then if you choose like maybe Kle Gene Then you go down to like MSN and DT and then you go down to like modular multiplication. Yeah. So like maybe the like we try to design something that's like quite general. Like I mean like general for the DKP skins is they are evolving like so fast. Yeah. And we still want to accelerate it, but we want to support the mainstream system and the potential updates. So like to handle that we first need to come up with with a vector machine. And this vector machine can basically handle this vectorized addition, multiplication and also modular multiplication. And yeah, so based on this like, based on this vector machine we have, I would say firmware part. So like we call it ZK isa ZK instruction set architecture. So this architecture we basically define several categories of instructions. And yeah, so the instructions there can be like ntt, like MSN like for the different curves and NDT for different ways. So we can basically using the instructions in the ZKI sum to construct I would say like the major kernel, msn, TT percent, mercury trend, all the other things. Yeah. So this well accounts for the majority of the current persistent. I mean like in terms of the proving time. But there's still like if you want to accelerate the KP faster then you need to accelerate every possible component in the kp. Yeah. So the long tail operation is like very complicated to handle and we are still like working on that. So some potential idea is to see we can have some cpu. By CPU I mean the ARM CPU cores on our chip to handle this long tail operation. Since you want to have a very satisfying performance, but you do not want maybe your PCBs to be plugged into some other ones like servers. Since the communication between these two things might be the bottleneck in the whole ZK proof generation. You want to achieve the. You want to have all the things like all the computation happen on chip to save some bandwidth there. Yeah. As we also mentioned in our Twitter, we observe that the major bottleneck actually lots of ZKP component is a bandwidth. Yeah. So if we can somehow avoid that, then we can also have better performance. So that's some rough idea. In summary, for the major components, the previously major components, we have a clear solution. But for the long tail ones, if we want to have all the computation hyper on chip, we are still exploring the solution for that. **Speaker B:** Got it. So just let me repeat it just to make sure I understand it. What you're saying is that it is correct to think about the ZK system as deconstructed down to the base mathematical primitives. And those are like super, super acceleratable. You've already kind of figured them out. What you're starting to realize is that the new or maybe the original bottlenecks of this system are no like they're not really about the actual mathematical primitives, the FFTs that you're running, anything like that. It's turning out that the bottlenecks are in the, the latency and the bandwidth of just like moving all the data to the correct chip or the correct part of the process. And what you're finding now is that the opportunity is to build these more integrated chips that contain like an FFT ASIC portion, but also might contain some other portions to accelerate the whole process and not just the advanced math. **Speaker A:** Right, right, right. Yeah. So like, so like previously like if you running the KDG like KDG plank, like say using Hello2 as a software backend, the Ms. And NDT accounts for 30 to accounts for 60 to 70% of the proof generation time for some like EVM circuit. Also for some other circuit. But I would say several months ago we found out using our FPGA system combined with a CPU where you do all the Ms. Entity on the FPGA system, but you do some other components, some previous minor components on the cpu. Actually the percentage of MSM plus NDT in the ZKEVM circuit shrink to, if I recall correctly, it shrinks to like 3 to 4%. It's down from 60 or 70%, like 2, 3 or 4%. So which means if you want to have better performance, you need to accelerate other fluffy components in the data generation. **Speaker B:** And so as you're working towards accelerating as you say the fluffier components, are you marching down a path that is creating chips for specific protocols? Like are you marching down the path of creating a KZG ASIC or are these asics still interesting primitives that can be built together into lots of different ZK protocols? **Speaker A:** Yeah, so our current design can support KZG fry stark folding skin all this main major components. Yeah, so like we like. Yeah so like if Sesik as a company just to design a hardware for the KZG based one or the, for the, or like more maybe like more generally for the EDP curve based one it will be actually like quite high risk for cycle. Like a lot of like players in the market are using the fly based ones or like some other proof system. So like we try to supports other pro system as well like in our common design. **Speaker B:** Got it. All right, so I want to shift the conversation here a little bit towards the process and the pain of manufacturing chips. So I think first can you just give us a like brief overview of what is the chip design and manufacture process look like. Like let's start from if I came to you as a company and said I want to accelerate this function, how do you go from this is the goal to this is what a design might look like to we've tested it, we know that it works to it's worth investing in a die. And then once you have a die, how do you get it into production and get thousands of chips? **Speaker A:** Okay, yeah. So the first thing is we have a spec. So the specific like define the algorithm, the input output and also the algorithm. And like then we write the RTO code for that. So basically it's a hardware coding part I'm not very familiar with. But like this code like it can be wrong like SPG and also on asic we basically need to design like we try to modulate the design like to come up with some motionless parts like say like we can maybe divide the computation into a lot of like sub components and for each sub component we name it as a P which is process elements, the most fundamental module in the chip. And so like we can say and after we finish the RTO coding then we will do some synthesizing on our end to see like what, what frequency we can run. Like the higher frequency the better. Yeah, so normally it can be running at maybe 1.5 GHz or something like that. So that's. So then we reach into a stage which we call RTO freeze. So like we freeze all this like front end code and then we will work with make for startups like if you are just maybe have around 20 people, you cannot afford to have a backend team to have a backend group in your team. So you will work with an external design service team who will convert your code into the real circuit on the board. The main goal of this network design servers is to improve the PPA which is like performance, power and area of your chip. And also since we are basically working on the computation part, you also need to integrate your computation part with the external ips. So you need to go to Synopsys or some other IP vendors to buy this PCIe DDR IP which is very expensive. Yeah. And after you buy the IP that you handle your codes and also you are working with a backend design service team to get a higher PPA for your chip. So that's the second stage and at the end of that stage we will have GTS2. You send this next GTS2 to some fab such as TSM C or Samsung to do the chip tip out, which will be also very expensive and you need to pay like you need to make the full payment in advance like maybe three or four months ahead of time to reserve the, the capacity to, to do the chip tip out. Yeah, yeah. So after, after the chip tip out is done, like which takes also like several months to process, you get your things. We are doing a full mask chip tape out. So we are going to get a wafer. The wafer, it has a lot of chips on it. We just cut the chips in piece. And then this time we come to the most exciting moments is to see whether you can bring up your chip, your chip like whether your chip is fully functional. So the bring up time takes like highly uncertain, maybe like one month, like two, seven months. Yeah, yeah. If, like, if you are like very happy you can bring up your chip, then the next stage is to say you need to pack your chip into the PCB, which is the 20 circuit board. Like you design your PCB and you have another vendor in the supply chain to manufacture your PCBs and so then you assemble the same thing to a machine and then unfortunately you can dispatch your machines to the buyers. **Speaker B:** So that's yeah, a couple months and many million dollars later. **Speaker A:** Yeah, that's like if you are lucky then. **Speaker B:** Got it. So to summarize what you said is you start with the spec and then what you guys do at CISIC is take the spec, design it in software, apply that software to FPGAs to make sure that it works and it's actually, you know, legitimate. And then you ship off this design to the backend developers who will like actually take your design and like write out the silicon, write out the wires, like what needs to be done. That plan goes to the chip manufacturer, which let's be real is just TCMC right now. And then you know, there's many subsets but essentially they create the chip for you based on the design. It comes back to you, you have to test it. And assuming the testing goes well, then it's time to send it to consumers or to customers. Is that right? **Speaker A:** Right. Yeah. So yeah. So like one more thing like, like the thing like we are doing after we finish all the RTO coding, we need to basically first run it on FPGA and some emulator to make sure our design is correct. We also play a lot with FPGA to explore the design space to get better. Yeah, but the fpga we try some experiment on fpga. But the fpga, if you want to try the experiment experiments, you also need to satisfy the resource restriction on fpga. So it's kind of a headache to get optimal performance and also to make sure your design is correct. **Speaker B:** And so as CISIC as a company grows, is the goal to vertically integrate more and more until you can do the entire design design and then just give it to TC tsmc or do you really like sitting in the like space of the front end development of the chip and then working with the supply chain to make it happen? **Speaker A:** Yeah, so I guess like in the beginning which is come, which is right now like we try to have the chip to go to the market maybe as soon as possible. So which means we can only handle the design parts. We actually we use FPGA to work with a lot of supply chain vendors. So for the FPGA we also like we have several customized FPGA machine. And the only thing that's not coming from us is FPGA chip which comes, which comes from AMD and all the other things. The PCBs, the machine, the cooling, the part delivery, all are designed by us. And also we work with supply chain extensively to make sure we can find reliable and trusted vendors to deliver the product in time. So I guess for now we rely a lot on the vendors. Yeah. To do some manufacturing for us. **Speaker B:** But the goal long term is to bring as much of that in house as possible as you grow in bandwidth and resources. **Speaker A:** Right. Yeah, so actually that's also something ongoing since we are right now working with PCB vendors and for some simulation we actually for the power, for the heat simulation, we have to do it by ourselves since like our design so like so specific that they haven't encountered something like this before. Yeah. **Speaker B:** So this question a little bit out there, but I'm very curious about manufacturing chips in 2023 because this whole genre is like kind of the molten core of a lot of the geopolitical tensions between us and China right now. And so I just kind of very broad question, answer this however you want, but do you find that the geopolitics and the news is actually creating enough noise to affect the way you're able to do business? Or is this like many things, one of those things where there's the news version of the world and then the business version of the world and they kind of operate non interactively. **Speaker A:** Yeah, so I guess maybe something in between. You need to be cautious about that whenever we want to work with vendors outside the U.S. we need to check with export control to make sure we are compliant on that part. As you can see, maybe if you are using a very advanced node to do the chip tip out, maybe you have to wait of quite, quite some time for that. So like, which means like we need to shift our maybe chip tip out to some like more mature and less competitive nodes. Yeah. To, to, to, to use those ones. Yeah. **Speaker B:** So in this same vein, the United States like within the last few years has, has made a major bet on chip manufacturing. There was the Chips act which put like tens if not hundreds of billions of dollars directly towards like new chip manufacturing or chip designing or chip anything in the U.S. one, is that something that's an opportunity for SISIG, but two, more holistically, do you see the U.S. becoming an actual competitive place to do a lot of this chip manufacturing or do you see this as kind of tilling it windmills and maybe a good idea but probably not going to make a real dent in how this industry works. **Speaker A:** I will say maybe in the first few years maybe the chip manufacturer was still happening in Taiwan as we can see like the TSMC due to. Yeah. So like the US like the chip factory in US they need to do a lot of experiments. Yeah. So maybe I'll just use example here. Maybe it's not a very appropriate example. Yeah. So like when Huawei. So Huawei is a Chinese company who is forbidden to do chip tip out in almost everywhere outside China. Yeah. So they use like a Chinese chip design chip like tape factory called smic. So actually SMIC is like previously SMIC used a lot of like the mining machines to try their process, try their techniques to make sure the thing they try out they are fully functional, fully correct. And after that they will have maybe after a lot of tryouts on the smarting machines. So Huawei then come to SMIC to do the real chip take power for their cell phone. So I guess for the United States. Yeah. So like I know some information like the chip design, the chip factory in United States is going a very similar route. Yeah. This is mining machines to try their process, try their technique. Yeah. Maybe after, after this next few years like the US chip factory should have the real capacity to do, to do some very advanced chip tip out. **Speaker B:** Got it. So you, you look at what's going on in the US and say like obviously it's chips short term, nothing's going to change. But there's actually some like real reasons to believe that there could be like a renaissance and maybe a real decentralization of chip manufacturing globally. **Speaker A:** Yes. Yeah, yeah, I believe that. Yeah. **Speaker B:** I mean, listen, the less important TSMC is, I think the less scary geopolitically the world is so very much a fan of new nodes in the chip manufacturing network. **Speaker A:** Yeah. **Speaker B:** Cool. All right, so I think we've covered what we can cover in manufacturing here. Let's shift to the little bit higher level of the stock. So I think we've talked a little bit about like we want to create chips in the end game that are, are accessible to hobbyists and to home people. So like, let's talk a little bit about like the, the business you're trying to create, right, is selling chips. Is there any part of you that wants to buy a bunch of your own chips and be a like kind of centralized proving farm that can be accessed like as a API, anything like that? **Speaker A:** Yes. We will also use part of our chips to provide the service to our partners right now. So we have a little bit more than 90zx project who want to use our servers. But right now due to our maybe shortage of GPU servers or FPGA servers, we can only provide service to a handful of that. But with our chip, maybe sometime next year, we can provide the service to all to maybe like to like. We account for a minor percentage of the computing power for the community. **Speaker B:** And so when the customers that you're working with right now, do you have any benchmark of. Let's say that they had the world's best cryptographers, but like the world's most average hardware engineers and like infrastructure people and they just implemented code on AWS in general, in CPUs, how much more performant and how much better can you do than a kind of a naive implementation in that way? **Speaker A:** I guess it also depends on the circuits. For instance, for the ZK GPT2 circuit, which is by Daniel Kong, using our FPGA combined with the CPU mode, as I mentioned before, we run the major component on FPGA while all the fluffy component on the cpu we can get a 58 times speed up over there like CPU performance. And the CPU is a 64 core CPU. So basically if they use a CPU to run the, to run the VK circuit, it takes more than 9,000 seconds I think. And using our approach we can reduce the proof generation time to 180 seconds. Yeah. **Speaker B:** Wow. **Speaker A:** Yeah, so that's one example. And for the leaky event circuit used by some layer tools, we can easily get a 5 times speed up over their GPU performance. GPU performance is usually 3 to 5 times faster than the CPU performance. **Speaker B:** And so this is with your current solution that is the FPGA plus the CPU kind of like packed together version, right? **Speaker A:** Yeah, yeah, yeah, that's right. **Speaker B:** So once your chip is ready and you're able to install it in the system, like what do you expect the performance to be, let's say on the ZKEVM one? **Speaker A:** Yeah. So I guess the current. Yeah, we basically we want to generate ZK even circuit in less than one second. I mean ZKEV circuit in less than one second. We want to achieve real time ZK proofing. Yeah. So which means like all the major component, major ZK circuit, the ZKEVM, ZK, ZKGPT2. Not sure about ZKGPT3 or GPT4, but for ZKGPT2, 3K we can definitely generate in real time. **Speaker B:** Got it. And this might be a little basic, but the important thing on the ZKEVM is that you need to generate the proof quickly enough and post it to Ethereum that all the state changes that just happen on the L2 make it to Ethereum and not like 20 minutes later or 22 hours later or like some inordinate amount of time. Right. Like that is the real impact that your technology can provide today. Just like for the very few use cases of ZK that are in practice. **Speaker A:** Right, right, right. Yeah. And other than that we also have, we are, we have a few customers who are designing the ZK Dex Decentralized exchange. Yeah, so like in that case you basically want us to generate the ZK proof as soon as possible since maybe if you wait more than one second then the price will change and. Yeah, and then you do some of your. So like that's another case and there's like the ZK bridge and the ZK coprocessor who also want us to generate the ZK proof in a configurable short of time. **Speaker B:** Yeah, yeah, I mean it's, it's super interesting and I think I'm a huge believer that when we get like 10 or 100 or thousand x improvements on efficiency, we like technologies evolve. Right. And the best example is the Internet. Right. And like we started with arpanet, which is like literally sending single characters to each other and then fast forward we have geocities and then fast forward we have Instagram and then like right now we are streaming high quality video, talking in real time. And it is that like order of magnitude improvement just in the like bandwidth that has like really transformed what the Internet is capable of. And so with that I, I'm so convinced that these order of magnitude improvements like people like you and Sisic are making or just the order of magnitude improvements, people like Succinct Labs or anyone that's just helping developers abstract out all of this complicated math are going to provide these order of magnitude improvements that transform the technology. But the big question mark is what does the world look like when we can do ZK instantly and trivially? Have you really spun your head around on in a world where CISIC is like this multibillion dollar behemoth and ZK compute is cheap and easy, what kind of world are we living in? **Speaker A:** Yeah, so the ZK can basically. So ZK is somehow independent of the blockchain. So they can basically provide a way for people to interact. It basically erase the layer of trust. You can use like you don't need to trust anyone. You can use like you just need to trust the mess. Like we can use ZK proof to communicate without concerning about the trust behind the things. And also the ZK has a lot of, I guess like other than the blockchain world, ZK can be also used in the maybe traditional world. So the traditional work, we can use ZK to fight like deep fake. We can use ZK to improve the TPS of some of these banks or some financial institutes. And also we can use ZK to make sure the traffic, the network traffic, they are satisfy the compliance using some ZK metabox technology. So I guess with the powerful hardware like we can find more applications of the case that have, that we probably couldn't imagine before. Yeah, so like as you just mentioned, like if like the, with the improvement of bandwidth in the Internet we can right now have like Instagram or even like TikTok like when I was like in Beijing like 10 years ago, like I also. So start application. It's very similar to tTalk but due to the slow bandwidth at that time, it can only support Instagram. So like that stuff was not a very successful one. Yeah, but like with right now the high speed, like we can do a lot of things. And also I believe with the high speed of the powerful leaking machine, we can also explore more applications on top of that. **Speaker B:** Yeah, for sure. And I know it's always like really tough to say like well what's going to happen once this technology is ready? I mean if anyone had that answer, we would not be on this podcast, we'd be founding a company right now. But I'm just so convinced that like, while the purpose and the energy around ZK today is about blockchain, I'm just looking around at the world changing and like, well, as AI gets better and every device out there becomes Internet connected and cars are driverless and Amazon's delivering drones or sorry, delivering packages with drones and like the world is becoming more connected, more digital, more autonomous. And I don't understand how any of this is possible without some sort of coordination system. And I think blockchain is a huge part of it, but it's not the whole part of it. I think the whole part of it is cryptography. **Speaker A:** I totally agree with that. And also maybe one more reason to start setting is to say I'm a cryptographer and I know that the cryptographers, they design very elegant systems in theory. And this system cannot be deployed in the real world is due to the efficiency and they can. It's just the one example. And we also have encryption and other things like. Yeah, so maybe one personal reason to starts Essex to bring this wonderful crypto systems to the real world. Maybe previously virus customized hardware, then firesign normal hardware. So that's also maybe a personal reason. Two stones, I think. Yeah. **Speaker B:** All right, Leo, thank you so much. I mean I could seriously go on for hours here and I really would love to sit down with you and talk to you about like what the ZK enabled future looks like. But I think this is a good time to wrap it up. So like before I let you go, can you just like let the audience know where can they find you if they want to learn more about Sisic, where can they find Sisic? And like most importantly, like, if you just want, if you like us are understanding that ZK is not only going to change the world, it is like the shelling point of the next like just technology revolution. How do you learn more and how do you get involved in zk? **Speaker A:** Yeah, I think the ZK community is a very like very friendly community. Like you can always try, you can always find a lot of materials to learn about the zk. You can always type in awesome ZK and you will find a lot of surveys, like a very long list of all the resources you need to learn to code in the uk. Yeah, it's a very, very, very good, good community and you can always find a lot of like YouTube videos on online to know about that. And if you want to find seismic, you can just try to type like size cysic and maybe like our Twitter handle is like cysic underscore XYZ So yeah, yeah, that should be the Twitter handle. So yeah, great. **Speaker B:** No, no, thank you so much. So yeah, please everyone go check out cisic. As I was telling Leo over the last few days, syscic is so important to what needs to happen in order to make ZK a real usable technology. And whether it's in just making the performance good enough for enterprise applications or I think even more importantly, wrestling this magic math into something that's like accessible by people without PhDs is what I like to call the Lord's work. So I just, I really appreciate what you're doing. I really appreciate what you're building for us. And man, I just, I hope to, to stay involved and watch you conquer the world. **Speaker A:** Thanks a lot. Yeah, thanks for, for inviting me to talk to talk about in, in the podcast. **Speaker B:** Yeah, of course. Well Leo, thank you so much and have a good rest of your day. **Speaker A:** Yeah, you too.